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[VHDL-FPGA-Verilog] CRC_module_of_FPGA

Description: 利用VHDL语言编写的一个crc功能模块，可下载到FPGA实现功能-use VHDL to prepare a crc function of the module, which can be downloaded to the FPGA functions
Platform: | Size: 3072 | Author: 黎飞飞 | Hits:

[VHDL-FPGA-Verilog] uartvhdl

Description: 一个在FPGA芯片上实现UART功能的vhdl源代码，提供了UART的集成-an FPGA chip to achieve UART function vhdl source code, providing integrated UART
Platform: | Size: 10240 | Author: 王利 | Hits:

[Other] taxiwork

Description: 介绍了基于FPGA的多功能计程车计价器的电路设计。该设计采用了可编程逻辑器件FPGA的ASIC设计，并基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程实现了整个系统的控制部分，整个自动控制系统由四个模块构成：秒分频模块、控制模块、计量模块和译码显示模块。该设计不仅仅实现了显示计程车计费的功能，其多功能表现在它可以通过选择键选择显示计程车累计走的总路程和乘客乘载的时间。计时、计程、计费准确可靠，应用于实际当中有较好的实用价值和较高的可行性。-introduced FPGA-based multifunctional taxi meter circuit design. The design using programmable logic device FPGA ASIC design, and for the super-high-speed VHDL hardware description language in the company Xilinx Spartan II Series 2 sc 200PQ208-5 chip programming of the control system as a whole, Automatic control the entire system from four modules : a seconds-frequency module, control module, metrology modules and decoding module. The design not only achieved a taxi showed Billing functions, Multifunctional its performance through its keypad revealed taxi taking the cumulative total journey of the passengers took the set time. Program, log, billing is accurate, reliable and practical application of them have good practical value and the higher the possibility.
Platform: | Size: 9216 | Author: 柑佬 | Hits:

[VHDL-FPGA-Verilog] dpram_fpga

Description: 这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
Platform: | Size: 2831360 | Author: 李伟 | Hits:

[VHDL-FPGA-Verilog] chengxu(vhdl)

Description: 这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序-VHDL and FPGA prepared by the computer serial communication procedures and an LED procedures
Platform: | Size: 548864 | Author: 黄鹏飞 | Hits:

[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)

Description: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Platform: | Size: 179200 | Author: 李中伟 | Hits:

[VHDL-FPGA-Verilog] USB11112

Description: USB的vhdl代码，具有很强的指导意义，对FPGA进行usb控制很有帮助！-USB vhdl code, which is of great guiding significance. the FPGA control usb helpful!
Platform: | Size: 140288 | Author: 温暖感 | Hits:

[VHDL-FPGA-Verilog] ps2_vhdl

Description: 利用vhdl实现FPGA芯片从PS2键盘读出数据(0-F) 并在数码管上显示 -use FPGA chip from the PS2 keyboard sensed data (0-F) and displayed on a digital control
Platform: | Size: 1024 | Author: 刘音 | Hits:

[Post-TeleCom sofeware systems] rs232_send

Description: rs232 vhdl程序 可以实行异步串行通信,这里只有send-rs232 vhdl procedures implemented asynchronous serial communication, here only send
Platform: | Size: 1024 | Author: 李湘宏 | Hits:

[Communication-Mobile] FPGA-OFDM-VHDL

Description:
Platform: | Size: 2767872 | Author: wang | Hits:

[Special Effects] Bersenham_line

Description: 程序设计与仿真 利用FPGA驱动LCD显示中文字符“年”的VHDL程序。 --文件名：lcd_driver.vhd。 --功能：FGAD驱动LCD显示中文字符“年”。 -program design and simulation using FPGA-driven LCD display Chinese characters "," VHDL program.-- File Name : lcd_driver.vhd.-- Function : FGAD driven LCD display Chinese characters "years."
Platform: | Size: 3072 | Author: 侯亮 | Hits:

[Communication-Mobile] kuopinvhdl

Description: 扩频系统的FPGA实现代码，相信对大家有很好的参考价值。-spread spectrum system FPGA code, I believe we have a good reference value.
Platform: | Size: 353280 | Author: 可难 | Hits:

[VHDL-FPGA-Verilog] vdevice

Description: 基于FPGA系统的数字电压表设计大范围，超精确的详细报告，共有40多页-FPGA-based system design digital voltage meter large-scale and ultra-precise details of the report, a total of over 40 pages
Platform: | Size: 140288 | Author: 刘嵘 | Hits:

[Other] FPGA_VHDL

Description: 这是一本有关FPGA的课本,对于刚接触FPGA的人来说非常有用-This is a textbook on the FPGA, FPGA for the fourth year is very useful
Platform: | Size: 3431424 | Author: 成应 | Hits:

[Other] VHDL_and_FPGA_design

Description: 本书的)4一个持色是从FPGA设计的角度出发．别祈了vHD巳语法的特点以及它们的正 确使用方沈，将初学者在运用vHDL语吉进行FPrjA设计中会遇到的疑惑，— 点拨清楚。 并纪合作者的多年FPGA设计经验，讲述厂许多EDA设计思想v并贯穿全书始终。 -the book) with a four color from the FPGA design point of view. Other vHD already have a prayer of the characteristics of grammar and the correct use of them, Shen Fang, beginners in the use of the phrase Kyrgyzstan vHDL for FPrjA design encounter puzzled-Inspiration clear. SUMMARY collaborators and FPGA design experience for many years, on many plants v EDA design ideas and has always run through the whole book.
Platform: | Size: 7979008 | Author: haopowan | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 677888 | Author: 钟方 | Hits:

[Picture Viewer] manticore

Description: 显卡中关于3D图形处理的源码，是VHDL版本的 喜欢硬件FPGA图像处理的可以看看，挺有意思-Graphics 3D graphics on the source, is like VHDL version of the FPGA hardware image processing can see quite interesting
Platform: | Size: 1686528 | Author: dido wang | Hits:

[Embeded-SCM Develop] vhdlcodes3

Description: FPGA/CPLD集成开发环境ISE使用详解实例－3-FPGA/CPLD integrated development environment IDE ISE example-3
Platform: | Size: 74752 | Author: 邓志斌 | Hits:

[Embeded-SCM Develop] vhdlcdes6

Description: FPGA/CPLD集成开发环境ISE使用详解实例－6-FPGA/CPLD integrated development environment IDE ISE example-6
Platform: | Size: 19456 | Author: 邓志斌 | Hits:

[VHDL-FPGA-Verilog] DDS_generator

Description: DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫屏锯齿波。频率可用键盘精确控制，设置多个挡位；可水平移动波形；-DDS sawtooth generator : Development Platform : maxplus+ FPGA functions : So output X Lu Ping Sawtooth. Keyboard can be used precision frequency control, multiple gear; Mobile waveform can level;
Platform: | Size: 852992 | Author: shiyj | Hits:
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